2018-10-10

IC Layout Design Engineer
Job Opportunity at Samaritan Technical Professional

Posted on Oct 10

http://www.samaritantech.com    928-759-0022

Location: San Diego, CA
Job Type: Full Time
Job ID: W4169405

We are seeking a layout design engineer to produce high-quality physical design for our transceiver product

ESSENTIAL FUNCTIONS OF THIS POSITION:
 
Layout and physical verification of high-speed, high-precision analog/mixed signal circuits in FinFET process—in addition to design of state-of-the-art silicon photonics integrated circuit layout
                                                                                                                                            
QUALIFICATIONS/SKILLS:
  • Proficient in using layout editing tools in the Cadence Virtuoso design environment
  • Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
  • Conceptual understanding of layout topics such as parasitics, matching, crosstalk, transistor layout dependent effects, latchup, IR drop, electromigration (EM), and deep nwell
  • Experience in chip-level floorplanning and analog block integration is desirable
  • Ability to use productivity-enhancing tools and design scripts to further automate tasks is also desirable
  • Can communicate clearly and effectively in English
 
EDUCATION & EXPERIENCE:
  • Minimum of 5 years of mask design experience in sub-micron CMOS (16nm or below preferred)
  • 3+ years of experience in high precision analog/mixed signal circuits, preferably in high-speed (more than 10GHz) application
 
90 day
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