Working in a highly collaborative multi-disciplinary team environment, you will perform functional verification of ASICs - FPGAs for mission critical military - defense system applications. You will create the verification plan in addition to developing the architecture and design. You will create run and-or post-processing scripts, as well as the overall methodology for a specific project (s). You will participate in the implementation of test benches. You will be self-directed and a good communicator.
* The ability to obtain and maintain a US DoD security clearance is required *
Title: Engineer (Senior --> Principal Levels)
Locations: Dallas, Texas (similar positions in Alabama, Arizona, Massachusetts and California)
Compensation: Salaried. Incentives. Profit sharing. Excellent benefit and relocation packages.
Required: BSEE-CE-PHY with 3+ years post academic design verification using Verilog, VHDL. System Verilog; Questa - ModelSim, VCS and-or NCsim; and Scripting.
Pluses: MSEE-CE-PHY. 7+ years ASIC - FPGA design-design verification. Current - prior DoD clearance. Linux. Universal Verification Methodology. UVM. VMM. OVM. DPI - PLI - FLI. Embedded systems. Digital Signal Processing. Communication protocols.
Other activities may include: Creation of Constrained Random Agents; Creation of Monitors, coverage collectors, and Scoreboards; Incorporation of available models that may exist as C-C++, Verilog or VHDL, etc., and-or creation of those models; Creation of functional coverage through use of assertions; Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan; Writing directed and constrained random tests in parallel with RTL designers to help achieve coverage goals; and use of trouble reports and bug tracking.